Architecture and Circuit - Level Design of anSRAM - Based Field - Programmable Gate

| Field-Programmable Gate Arrays (FPGAs) are now widely used for the implementation of digital systems and many commercial architectures are available. Although the literature and data books contain detailed descriptions of these architectures, there is very little information on how the high-level architecture was chosen and no information on the circuit-level or physical design of the devices. This paper describes the design of an SRAM-programmable FPGA, starting from the high-level architecture through the circuit design issues to the physical layout. The logic block and routing architecture of the FPGA was determined through experimentation with benchmark circuits and custom-built CAD tools. The resulting logic block is an asymmetric tree of four-input lookup tables that are hard-wired together and a segmented routing architecture with a carefully chosen segment length distribution. At the circuit design level, we address area-speed trade-oos in the design of the logic block circuits and in the connections between the logic and the routing structure. All commercial FPGA designs are done using full-custom hand layout to obtain absolute minimum die sizes. This is both labor and time-intensive. We propose a design style with a mini-tile that contains a portion of all the components in the logic tile, resulting in less full-custom eeort. The mini-tile is replicated in a 4 4 array to create a macro tile. The mini-tile is optimized for layout density and speed, and is customized in the array by adding appropriate vias. This technique also permits easily changing the hard-wired connections in the logic block architecture, and the segmen-tation length distribution in the routing architecture.